1. Field of the Invention
This invention generally relates to carriers for integrated circuits and the like and more specifically to such carriers that, during manufacture and assembly operations position such circuits, protect them from mechanical and electrical damage and facilitate their testing.
2. Description of Related Art
Semiconductor devices have matured from simple circuit elements into complex components, and this maturation has been accompanied by an increase in the complexity of handling these components during assembly and testing operations. For example, simple, discrete components such as transistors, diodes and the like, either were soldered directly into a circuit or were held in component sockets to facilitate replacement. With the advent of more sophisticated assembly equipment and procedures, it became advantageous to position these devices mechanically and then to solder groups of terminals associated with plural components to a circuit board during a single soldering operation. When these circuit boards failed, it was still possible to replace individual components because the replacement procedures were straightforward as each component had only a few terminals that could be cut and removed.
With current technology, semiconductor devices include expensive integrated circuits and like components with a large number of terminals These integrated circuits often are located on multiple layer circuit boards. They have become subject to damage from a number of external influences such as mechanical shock and discharges of accumulated electrostatic charge. Thus, the procedures for handling such components are critical Moreover, the increased density of such components on circuit boards and their costs have led to the development of component testing prior to assembly. These procedures are also necessary because in many situations it no longer is economically feasible to replace defective components. Often an entire circuit board with a number of valuable integrated circuits may be discarded even if a single component on the board fails.
The need to protect integrated circuits and test them individually led to the advent of chip carriers. Chip carriers are special enclosures or packages that house an integrated circuit or the like during processing, production, testing and assembly operations. More specifically, a typical chip carrier orients an integrated circuit during the production process, assures proper placement and alignment of terminals for testing and for insertion into a printed circuit board. They eliminate stresses from the terminals and seals in such integrated circuits. More recently, chip carriers have been constructed to dissipate electrostatic charges that otherwise can accumulate on a component. There are several general approaches to the chip carrier design that seek to provide these various functions.
In accordance with one general approach, a carrier body supports an integrated circuit. An electrical shorting mechanism or insert contacts all the terminals to dissipate any electrostatic charge. Other mechanisms displace the shorting bar or insert from the terminals during testing operations. The following U.S. Letters Patent depict various specific embodiments that incorporate this general approach.
U.S. Pat. No. 3,653,498 (1972) Kisor PA1 U.S. Pat. No. 3,746,157 (1973) l'Anson PA1 U.S. Pat. No. 4,026,412 (1977) Henson PA1 U.S. Pat. No. 4,549,651 (1985) Alemanni PA1 U.S. Pat. No. 4,677,520 (1987) Price PA1 U.S. Pat. No. 4,706,161 (1987) Buckingham PA1 U.S. Pat. No. 4,725,918 (1988) Bakker
Kisor discloses a carrier formed of a carbon-embedded plastic with a shorting member that contacts all the terminals. The shorting member must be removed prior to testing. L'Anson discloses an analogous structure with a shorting member that falls away from the terminals during testing. Buckingham discloses a shorting bar held across accessible terminals; the bar is withdrawn for testing. Bakker discloses a chip carrier with an insert that avoids electrostatic discharges; the insert must be removed before testing occurs.
An insulating base member in Henson supports an integrated circuit housing on a metallic heat sink; a cover overlies the housing The insulting base member supports extensions of the terminals that extend beyond the cover. Alemanni discloses a carrier for a pin grid array circuit with a base member having a plurality of apertures formed through removable carrier inserts to adapt the carrier to a variety of packages. Neither Henson nor Alemanni discusses problems associated with the accumulation of electrostatic charges. Price discloses a device that protects a component from electrostatic discharges by positioning the device in an ionizable gas.
U.S. Pat. No. 4,765,471 of Robert Murphy, that is titled Electrical Component Carrier and assigned to the same assignee as the present invention, discloses a chip carrier that performs a number of desirable functions without the need for shorting bars, inserts or related apparatus as shown in the foregoing references. In accordance with this patent, a plate assembly, comprising an insulating plate sandwiched between two conductive plates, supports a pin grid array (PGA) component. Apertures through all the plates receive the integrated circuit terminals, these apertures being in register through the plate assembly. The diameter of each aperture in the insulating plate is less than the corresponding diameters in the conductive plates, so plate assembly electrically isolates each terminal, but enables access to each terminal for testing below the plate assembly. A conductive cover overlies and retains the component in the carrier in a fixed position. Peripheral skirts or walls that circumscribe e plate assembly protect the component and its terminals from mechanical damage. The existence of conductive surfaces covering all the insulating materials prevents the accumulation of electrostatic charge.
When components are handled without any electrostatic protection, discharges of several thousands of volts can occur. The structure disclosed in the foregoing U.S. Pat. No. 4,765,471 limits and even eliminates electrostatic discharges. Although such protection necessary for a number of integrated circuits and other components, it has been determined that a class of components, including integrated circuits, exist that can withstand discharges of hundreds of volts. For components in this class, it was difficult to justify the additional manufacturing costs associated with extensively covering all insulating portions of a chip carrier with a conductive material. Moreover, structures such as shown in U.S. Pat. No. 4,765,471, seem limited to use with a single package style, such as a pin grid array (PGA) package. The application of such approaches to other package types, such as flatpack and transistor outline packages was not clearly evident.